// Copyright (c) 2014-2023 All rights reserved
// *********************************************************************************
// Project Name : 
// Author       : Dark
// Create Time  : 2023-01-27 16:53:04
// Revise Time	: 2023-01-27 16:53:04
// File Name    : ram.sv
// Abstract     :

`include "defines.svh"

module ram #(
	parameter MEMDEEP = 4096 -1 
)(
 	input [3:0]      	byteena,
 	input [31:0]     	din,
 	input [31:0]     	rdaddr,
 	input            	rdclk,
  	input            	rden,
 	input [31:0]     	wraddr,
 	input             	wrclk,
 	input             	wren,
 	output reg  [31:0]	dout);






//=================================================================================
// Body
//=================================================================================



`ifdef FPGA_SYN
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
	ram_4096 u_ram_4096 (
	  .clka(wrclk),    // input wire clka
	  .ena(wren),      // input wire ena
	  .wea(byteena),      // input wire [3 : 0] wea
	  .addra(wraddr),  // input wire [11 : 0] addra
	  .dina(wrdata),    // input wire [31 : 0] dina
	  .clkb(rdclk),    // input wire clkb
	  .enb(rden),      // input wire enb
	  .addrb(rdaddr),  // input wire [11 : 0] addrb
	  .doutb(dout)  // output wire [31 : 0] doutb
	);
`else 
	localparam BYTESIZE	= 8;

	reg		[31:0]	mem [0:MEMDEEP];
	wire	[31:0]	tempout;
	wire	[31:0]	tempin;
	genvar i;
	generate
		for (i=0;i<4;i++)
			assign tempin[(i+1)*BYTESIZE-1:i*BYTESIZE]   = (byteena[i])? 
															din[(i+1)*BYTESIZE-1:i*BYTESIZE]  
														:	tempout[(i+1)*BYTESIZE-1:i*BYTESIZE];
	endgenerate
	assign  tempout	=	mem[wraddr];
	
	always_ff@(posedge rdclk)
		if(rden)
		  dout <= mem[rdaddr];
	
	always@(posedge wrclk)    // memory array can't use always_ff
		if(wren)
		  mem[wraddr]<=tempin;
`endif	
endmodule

